1. Field of the Invention
The present invention relates to a method of forming minute patterns in a semiconductor device and, more particularly, to a method of forming minute patterns in a semiconductor device by double patterning.
2. Description of the Related Art
Minute patterns are essential for high integration of a semiconductor device. In order to integrate many devices in a small region, the size of each device has to be small, thus, a feature P, the sum of a width of each pattern to be formed and a distance between each pattern, has to be small. Recently, due to a sharp decrease of a device design rule, a photolithography process of forming a pattern, in particular, a line and space pattern to realize a semiconductor device, has resolution limits. As the result of the resolution limits, there are limitations to forming a pattern having a minute feature.
In order to overcome the resolution limits in the photolithography process, a method of forming minute patterns by double patterning has been presented.
FIGS. 1A through 1E illustrate cross-sectional views of stages describing a conventional method of forming a semiconductor device.
Referring to FIG. 1A, a first oxide layer 14 and a poly-silicon layer 15 are sequentially stacked on a substrate 11. Adequate material layers may be further formed between the substrate 11 and the first oxide layer 14. For example, a gate insulating layer 12 and a tungsten layer 13 may be sequentially formed on the substrate 11.
Photoresist layer patterns 16-1, 16-2, and 16-3 are formed on the poly-silicon layer 15. A plurality of photoresist layer patterns 16-1 separated from each other by a uniform distance and each having a width corresponding to a first feature size 1f is formed between the photoresist layer pattern 16-2 and the photoresist layer pattern 16-3. For example, the photoresist layer pattern 16-2 is disposed at a position corresponding to a GSL (Ground Select Line), the photoresist layer pattern 16-3 is disposed at a position corresponding to an SSL (String Select Line), and the photoresist layer patterns 16-1 are disposed at positions respectively corresponding to word lines.
The photoresist layer patterns 16-1, 16-2, and 16-3 are separated from each other by a uniform distance, that is, they are separated from each other by a third feature size 3f that is three times as wide as the first feature size 1f. Thus, the photoresist layer pattern 16-2 and the photoresist layer pattern 16-3 are individually separated from their most adjacent photoresist layer pattern 16-1 by the third feature size 3f. 
Referring to FIG. 1B, the photoresist layer patterns 16-1, 16-2, and 16-3 are used as an etching mask to etch the poly-silicon layer 15 to form first poly-silicon layer patterns 15a-1, 15a-2, and 15a-3. The first poly-silicon layer patterns 15a-1, 15a-2, and 15a-3, which are adjacent to each other, are separated from each other by the third feature size 3f. 
Referring to FIG. 1C, a second oxide layer 17 is formed to uniformly cover the first poly-silicon layer patterns 15a-1, 15a-2, and 15a-3. A thickness of the second oxide layer 17 is the same as the first feature size 1f. Thus, a distance between each adjacent second oxide layers 17 is the same as the first feature size 1f. 
Referring to FIG. 1D, a plurality of second poly-silicon layer patterns 18 individually fill a space between each adjacent second oxide layers 17. If an even number 2n of the first poly-silicon layer patterns 15a-1 are formed, then an odd number 2n+1 of the second poly-silicon layer patterns 18 are formed. If an odd number 2n−1 of the first poly-silicon layer patterns 15a-1 are formed, then an even number 2n of the second poly-silicon layer patterns 18 are formed. Thus, an odd number of the first poly-silicon layer patterns 15a-1 and the second poly-silicon layer patterns 18, each having the first feature size 1f, are formed between the first poly-silicon layer pattern 15a-2 corresponding to the GSL and the first poly-silicon layer pattern 15a-3 corresponding to the SSL. Thus, the conventional method has a problem in forming an even number of the first poly-silicon layer patterns 15a-1 and the second poly-silicon layer patterns 18, each having the first feature size 1f, between the first poly-silicon layer pattern 15a-2 corresponding to the GSL and the first poly-silicon layer pattern 15a-3 corresponding to the SSL. In order to use an even number of the first poly-silicon layer patterns 15a-1 and the second poly-silicon layer patterns 18, an odd number of patterns randomly selected among the first poly-silicon layer patterns 15a-1 and the second poly-silicon layer patterns 18 have to be used as dummy patterns. However, this method is not desirable since a symmetric structure is not achieved.
FIG. 5 illustrates a plane view of a semiconductor device formed using a conventional double patterning method. Referring to FIG. 5, an odd number of insert patterns are formed between a first basic pattern (e.g., a GSL pattern) and a second basic pattern (e.g., an SSL pattern). In the case where an even number of insert patterns among the odd number of insert patterns are used as word line patterns WL0 through WL31, two dummy patterns should be used between the first basic pattern (e.g., the GSL pattern) and the word line pattern WL0, and one dummy pattern should be used between the second basic pattern (e.g., the SSL pattern) and the word line pattern WL31. Such an asymmetric structure may cause an undesirable result in a gate operation.
Referring back to FIG. 1E, the first poly-silicon layer patterns 15a-1, 15a-2, and 15a-3, and the second poly-silicon layer patterns 18 are used as an etching mask to etch the second oxide layer 17 and a first oxide layer 14a. After that, the tungsten layer 13 and the gate insulating layer 12 are etched to form a tungsten layer pattern 13a-2 and a gate insulating layer pattern 12a-2. As the result of the etching, an odd number of word line patterns 14b-1 are formed between a GSL 14b-2 and an SSL 14b-3.
Accordingly, there is a need to develop a method of forming an even number of insert patterns between a first basic pattern and a second basic pattern by double patterning.